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Breaking the Memory Wall: Near-Data Processing for Hyperscale Applications (Dr. Gwangsun Kim (김광선))
작성자
첨단컴퓨팅학부
작성일
2025.01.09
최종수정일
2025.01.09
분류
세미나
링크URL
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일시: 2025. 1. 15.(수) 17:00-18:00
장소: 제1공학관 A528

Title: Breaking the Memory Wall: Near-Data Processing for Hyperscale Applications

Presentor: Dr. Gwangsun Kim (김광선)
Assistant Professor / Department of Computer Science and Engineering at POSTECH

Abstract: The memory wall has long been recognized as a critical challenge in high-performance systems, and it has recently become even more significant due to the exponential growth of machine learning model sizes. Meanwhile, recent advancements in interconnect technology, such as Compute Express Link (CXL), enable scalable memory system designs to address the memory capacity wall. Moreover, by offloading data and computation to CXL memory expanders to realize Near-Data Processing (NDP), the memory bandwidth wall can also be effectively mitigated. However, designing such a system should be done carefully, considering various design aspects that can affect the practicality of the solution.
In this talk, I will discuss key considerations and directions for building a practical NDP system architecture, including general-purpose computing, low-latency host communication, standard compliance, and cost-effectiveness. I will then present our recent work on an NDP architecture called Memory-Mapped NDP (M²NDP). M²NDP consists of two components: 1) Memory-Mapped Function (M²func), which enables low-latency host-device communication by addressing the overhead of conventional ring buffer-based task offloading, and 2) Memory-Mapped μthreading (M²μthread), a general-purpose, cost-effective NDP unit architecture that aims to maximize resource utilization by hybridizing CPU and GPU architectures. Finally, I will briefly outline future research directions based on the M²NDP architecture.

Bio: Gwangsun Kim is an Assistant Professor in the Department of Computer Science and Engineering at POSTECH. Previously, he worked as a Senior Research Engineer and Senior Performance Engineer at Arm Inc. He received the B.S. degrees in Electronic and Electrical Engineering and Computer Science and Engineering from POSTECH in 2010, and the M.S. and Ph.D. degrees in Computer Science from KAIST in 2012 and 2016, respectively. He has worked on various areas of computer architecture and systems, including memory systems, parallel architectures, GPU computing, systems for machine learning, near-data processing, networking, deep learning compiler, and simulation methodology. He is particularly interested in designing practical architectures for high-performance and scalable systems.